Video image display apparatus and buffer management method for video image display apparatus

ABSTRACT

A buffer management method implemented in a video image display apparatus for displaying images, including: controlling a write address in a buffer for writing input data thereto; controlling a read address in the buffer for reading display data therefrom; comparing the write address and read address; and managing a transmission of the display data to a spatial light modulator (SLM) based on a comparison result of comparing the write address to the read address.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Non-provisional Application claiming a Prioritydate of Dec. 4, 2007 based on a previously filed Provisional Application61/005,337, a Non-provisional patent application Ser. No. 11/121,543filed on May 3, 2005 issued into U.S. Pat. No. 7,268,932 and anotherNon-provisional application Ser. No. 10/698,620 filed on Nov. 1, 2003.The application Ser. No. 11/121,543 is a Continuation In Part (CIP)Application of three previously filed Applications. These threeApplications are Ser. No. 10/698,620 filed on Nov. 1, 2003, Ser. No.10/699,140 filed on Nov. 1, 2003 now issued into U.S. Pat. No.6,862,127, and Ser. No. 10/699,143 filed on Nov. 1, 2003 now issued intoU.S. Pat. No. 6,903,860 by the Applicant of this Patent Applications.The disclosures made in these Patent Applications are herebyincorporated by reference in this Patent Application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus and a method, both forcontrolling a spatial light modulator (SLM) comprised in a video imagedisplay apparatus. More particularly, the present invention relates to avideo image display apparatus implemented with multiple spatial lightmodulators for reflecting and modulating light of different colorscontrolled to project the lights with specially arranged time sequences.

2. Description of the Related Art

Even though there have been significant advances made in recent years inthe technology of implementing electromechanical micromirror devices asspatial light modulators (SLM), there are still limitations anddifficulties when these are employed to display high quality images.Specifically, when the display images are digitally controlled, thequality of the images is adversely affected because the images are notdisplayed with a sufficient number of gray scale gradations.

Electromechanical mirror devices are drawing a considerable amount ofinterest as spatial light modulators (SLM). The electromechanical mirrordevice consists of a mirror array arranging a large number of mirrorelements. In general, the number of mirror elements range from 60,000 toseveral millions and are arranged on the surface of a substrate in anelectromechanical mirror device.

Refer to FIG. 1A for a digital video system 1 as disclosed in a relevantU.S. Pat. No. 5,214,420, which includes a display screen 2. A lightsource 10 is used to generate light energy to illuminate display screen2. Light 9 is further concentrated and directed toward lens 12 by mirror11. Lens 12, 13, and 14 serve a combined function as a beam collimatorto direct light 9 into a column of light 8. A spatial light modulator 15is controlled by a computer through data transmitted over data cable 18to selectively redirect a portion of the light from path 7 toward lens 5to display on screen 2. The SLM 15 has a surface 16 that includesswitchable reflective elements, e.g., micro-mirror devices 32 withelements 17, 27, 37, and 47 as reflective elements attached to a hinge30, as shown in FIG. 1B. When element 17 is in one position, a portionof the light from path 7 is redirected along path 6 to lens 5 where itis enlarged or spread along path 4 to impinge the display screen 2 so asto form an illuminated pixel 3. When element 17 is in another position,light is not redirected toward display screen 2 and hence pixel 3 wouldbe dark.

Each of the mirror elements constituting a mirror device functions as aspatial light modulator (SLM), and each mirror element comprises amirror and electrodes. A voltage applied to the electrode(s) generates aCoulomb force between the mirror and the electrode(s), making itpossible to control and incline the mirror. The inclined mirror is“deflected” according to a common term used in this patent applicationfor describing the operational condition of a mirror element.

When a mirror is deflected with a voltage applied to the electrode(s),the deflected mirror also changes the direction of the reflected lightin reflecting an incident light. The direction of the reflected light ischanged in accordance with the deflection angle of the mirror. Thepresent patent application refers to the light reflected to a projectionpath designated for image display as “ON light”, and refers to a lightreflected in a direction away from the designated projection path forimage display as “OFF light”. When only a portion of the reflected lightis directed in the ON light direction and the light reflected by themirror to the projection path is of lesser intensity than the “ONlight”, it is referred to as “intermediate light”.

The present patent application defines an angle of rotation along aclockwise (CW) direction as a positive (+) angle and that of acounterclockwise (CCW) direction as a negative (−) angle. A deflectionangle is defined as zero degrees (0°) when the mirror is in the initialstate.

The on-and-off states of a micromirror control scheme, such as thatimplemented in the U.S. Pat. No. 5,214,420 and by most conventionaldisplay systems, limit image display quality. This is because theapplication of a conventional control circuit limits the gray scale (PWMbetween ON and OFF states) by the LSB (least significant bit, or theleast pulse width). Due to the ON-OFF states implemented in conventionalsystems, there is no way to provide a pulse width shorter than the LSB.The least brightness, which determines the gray scale, is the lightreflected during the least pulse width. A limited gray scale leads tolower image quality.

In FIG. 1C, a circuit diagram of a control circuit for a micro-mirroraccording to U.S. Pat. No. 5,285,407 is presented. The control circuitincludes memory cell 32. Various transistors are referred to as “M*”where * designates a transistor number and each transistor is aninsulated gate field effect transistor. Transistors M5, and M7 arep-channel transistors; transistors, M6, M8, and M9 are n-channeltransistors. The capacitances, C1 and C2, represent the capacitive loadspresented to memory cell 32. Memory cell 32 includes an access switchtransistor M9 and a latch 32 a, which is the basis of the Static RandomAccess switch Memory (SRAM) design. All access transistors M9 in a rowreceive a DATA signal from a different bit-line 31 a. The particularmemory cell 32 to be written is accessed by turning on the appropriaterow select transistor M9, using the ROW signal functioning as aword-line. Latch 32 a is formed from two cross-coupled inverters, M5/M6and M7/M8, which permit two stable states. State 1 is Node A high andNode B low and state 2 is Node A low and Node B high.

The mirror is driven by a voltage applied to the landing electrode andis held at a predetermined deflection angle on the landing electrode. Anelastic “landing chip” is formed on the portion of the landing electrodethat comes into contact with the mirror, and assists in deflecting themirror towards the opposite direction when the deflection of the mirroris switched. The landing chip is designed to have the same potential asthe landing electrode so that a shorting is prevented when the landingelectrode is in contact with the mirror.

Each mirror formed on a device substrate has a square or rectangularshape, and each side has a length of 4 to 15 um. In this configuration,a portion of the reflected light is reflected not from the mirrorsurface but from the gaps between the mirrors or other surfaces of themirror device. These “unintentional” reflections are not applied toproject an image and are inadvertently generated. The contrast of thedisplayed image is degraded due to the interference from theseunintentional reflections generated by the gaps between the mirrors. Inorder to overcome this problem, the mirrors are arranged on asemiconductor wafer substrate with a layout to minimize the gaps betweenthe mirrors. One mirror device is generally designed to include anappropriate number of mirror elements, wherein each mirror element ismanufactured as a deflectable mirror on the substrate for displaying apixel of an image. The appropriate number of elements for displaying animage is configured in compliance with the display resolution standardaccording to the VESA Standard defined by the Video ElectronicsStandards Association or by television broadcast standards. When amirror device is configured with the number of mirror elements incompliance with WXGA (resolution: 1280 by 768) defined by VESA, thepitch between the mirrors of the mirror device is 10 μm, and thediagonal length of the mirror array is about 0.6 inches.

The control circuit, as illustrated in FIG. 1C, controls the mirrors toswitch between two states, and the control circuit drives the mirror tooscillate to either an ON or OFF deflected angle (or position) as shownin FIG. 1A.

The minimum intensity of light reflected from each mirror element forimage display, i.e., the resolution of gray scale of image display for adigitally-controlled image display apparatus, is determined by the leastlength of time that the mirror may be controlled to stay in the ONposition. The length of time a micromirror is in an ON position iscontrolled by a multiple bit word. FIG. 1D shows the “binary timeintervals” when controlling micromirrors with a four-bit word. As shownin FIG. 1D, the time durations have relative values of 1, 2, 4, 8, whichin turn define the relative brightness for each of the four bits, where“1” is the least significant bit and “8” is the most significant bit.According to the control mechanism as shown, the minimum controllabledifferences between gray scales for showing different levels ofbrightness is a represented by the “least significant bit” thatmaintains the micromirror at an ON position.

For example, assuming n bits of gray scales, one time frame is dividedinto 2^(n)-1 equal time periods. For a 16.7-millisecond frame period andn-bit intensity values, the time period is 16.7/(2^(n)-1) milliseconds.

Among conventional display apparatuses, comprised of one SLM asdescribed above, a color display is projected by changing over, in atime sequence, the colors of light to be displayed onto a screen using awheel, which is known as a color wheel and which comprises a pluralityof color filters (e.g., red (R), green (G) and blue (B) color filters)possessing different wavelength bands of transmission light in aplurality of regions, and a plurality of laser lights (e.g., R, G and Blaser lights) that emit the lights of different wavelength bands.

Such a display apparatus, however, attains a color display by projectingeach of a plurality of color lights in a time sequence, and therefore adistortion phenomenon known as a “color breakup” (or a rainbow effect)is known to occur. A color breakup occurs when a rainbow-like image isinstantly visible when, for example, a viewer shifts his or her point offocus on the screen.

Accordingly, it is desirable to design a display apparatus such that acolor display is projected through the projection of a plurality ofcolor lights onto a screen in a time sequence, while suppressing theoccurrence of the above described color breakup.

SUMMARY OF THE INVENTION

In consideration of the situation described above, the present inventionaims at providing an apparatus and method, both for suppressing theoccurrence of the color breakup phenomenon in a display apparatusimplementing a color display by projecting a plurality of color lightsonto a screen in a time sequence.

In order to accomplish the aim noted above, an apparatus according to anaspect of the present invention is a video image display apparatusdisplaying a video image in accordance with a video image signal,including: a buffer for storing data; a pointer generation unit forgenerating a write pointer, that is, a pointer used for writing data tothe buffer, and a read pointer, that is, a pointer used for reading datafrom the buffer; a comparison unit for comparing the value of the writepointer and that of the read pointer; and a data readout unit forcontrolling the read pointer on the basis of the result of a comparisonperformed by the comparison unit.

A method according to one aspect of the present invention is a buffermanagement method used for a video image display apparatus, including:controlling a write position, that is, the position of a buffer forwriting input data thereto; controlling, a read position, that is, theposition of the buffer for reading display data therefrom; comparing thewrite position and read position; and managing display data to betransmitted to a spatial light modulator (SLM) on the basis of thecomparison result.

An apparatus according to another aspect of the present invention is avideo image display apparatus displaying a video image in accordancewith a video image signal, including: a plurality of spatial lightmodulators (SLMs); and a buffer for storing data on the basis of thevideo image signal, wherein data which is read from the bufferasynchronous with a data writing to the buffer is transmitted to atleast one of the SLMs, and data which is read from the buffer insynchronous with a timing of a data writing to the buffer is transmittedto the rest of the SLMs.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is described in detail below with reference to thefollowing Figures.

FIGS. 1A and 1B are, respectively, a functional block diagram and a topview of a portion of a micromirror array implemented as a spatial lightmodulator for a digital video display system of a conventional displaysystem disclosed in a prior art patent.

FIG. 1C is a circuit diagram for showing a prior art circuit forcontrolling a micromirror to position at an ON and/or OFF state of aspatial light modulator.

FIG. 1D is diagram for showing the binary time intervals for a four bitgray scale.

FIG. 2A is a diagram illustrating an exemplary optical comprisal of avideo image display apparatus according to a first preferred embodiment;

FIG. 2B is a side view diagram of a color synthesis optical system as apart of the optical comprisal shown in FIG. 2A;

FIG. 2C is a front view diagram of the color synthesis optical system, apart of the optical comprisal shown in FIG. 2A;

FIG. 3 is a functional block diagram illustrating the systemconfiguration of a video image display apparatus comprising a timingcontrol apparatus according to the first embodiment;

FIG. 4 is a functional block diagram showing, in detail, the internalconfiguration of a sequencer according to the first embodiment;

FIG. 5 is a flow chart showing, in detail, the operation of a dataoutput control unit according to the first embodiment;

FIG. 6 is a timing chart showing, in detail, an exemplary operation ofthe data output control unit shown in FIG. 5;

FIG. 7 is a flow chart showing, in detail, the operation of a pointercontrol unit according to the first embodiment;

FIG. 8 is a first timing chart showing an exemplary operation of thepointer control unit shown in FIG. 7;

FIG. 9 is a second timing chart showing an exemplary operation of thepointer control unit shown in FIG. 7;

FIG. 10 is a diagram illustrating the optical comprisal of a video imagedisplay apparatus comprising an SLM control apparatus according to asecond preferred embodiment;

FIG. 11 is a functional block diagram illustrating the system comprisalof a video image display apparatus comprising an SLM control apparatusaccording to the second embodiment;

FIG. 12 is a diagram illustrating the circuit configuration of eachmirror element;

FIG. 13A is a diagram describing the ON control for a mirror;

FIG. 13B is a diagram describing the OFF control for a mirror;

FIG. 13C is a diagram describing the oscillation control for a mirror;

FIG. 14A is a first diagram showing an exemplary control for two SLMsperformed by an SLM controller;

FIG. 14B is a first diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 15A is a second diagram showing an exemplary control for two SLMsperformed by an SLM controller;

FIG. 15B is a second diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 16A is a third diagram showing an exemplary control for two SLMsperformed by an SLM controller

FIG. 16B is a third diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 17A is a fourth diagram showing an exemplary control for two SLMsperformed by an SLM controller

FIG. 17B is a fourth diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 18A is a fifth diagram showing an exemplary control for two SLMsperformed by an SLM controller

FIG. 18B is a fifth diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 19A is a sixth diagram showing an exemplary control for two SLMsperformed by an SLM controller

FIG. 19B is a sixth diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 20A is a seventh diagram showing an exemplary control for two SLMsperformed by an SLM controller

FIG. 20B is a seventh diagram showing an exemplary control for two SLMsperformed by an SLM controller in a video image display apparatuscomprising a lamp light source and a color wheel;

FIG. 21 is a first diagram showing an exemplary control for two SLMs andlaser lights to be incident to the two SLMs;

FIG. 22 is a second diagram showing an exemplary control for two SLMsand laser lights to be incident to the two SLMs;

FIG. 23 is a first diagram showing an exemplary control for two SLMs andlaser lights to be incident to the two SLMs and also showing the colorsof output lights (i.e., projection lights) that are projected onto ascreen by the two SLMs; and

FIG. 24 is a second diagram showing an exemplary control for two SLMsand laser lights to be incident to the two SLMs and also showing thecolors of output lights (i.e., projection lights) that are projectedonto a screen by the two SLMs.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention are described belowwith reference to the accompanying drawings.

FIG. 2A is a functional block diagram for illustrating a video imagedisplay apparatus that includes optical components according to a firstpreferred embodiment of the present invention. Specifically, FIG. 2Ashows a video image display apparatus includes a color synthesis opticalsystem for illustrating the color synthesis process with a top view anda rear view. FIG. 2B is a side view diagram for illustrating the opticaltransmissions of the same color synthesis optical system. FIG. 2C is afront view diagram of the color synthesis optical system.

The video image display apparatus according to the present embodimentcomprises a device package 102 for containing two spatial lightmodulators (SLMs) 101 (i.e., 101 a and 101 b) therein. The video imagedisplay apparatus further includes a color synthesis optical system 103,a light source optical system 104, a light source 105, and a projectionlens 106. More specifically, each of the two SLMs 101 is implementedwith a micromirror device that includes a plurality of mirror elementsconfigured as two-dimensional mirror array. Furthermore, the lightsource 105 is a lamp light source, e.g., a high-pressure mercury lamp ora xenon lamp.

Two SLMs 101 a and 101 b accommodated in the device package 102 arefixed within the rectangular package, with the rectangular contour ofthe SLM inclined by approximately 45 degrees within the horizontal planerelative to each side of the device package 102. The color synthesisoptical system 103 is placed on the device package 102.

The upper part of the diagram FIG. 2A shows a rear view of the colorsynthesis optical system 103, while the lower part of the diagram showsa top view of the color synthesis optical system 103.

The color synthesis optical system 103 comprises right-angle trianglecolumnar prisms 107 and 108 that are adhesively attached along thelength of each prism to constitute an approximate equilateral trianglecolumn. The color synthesis optical system 103 further comprises of aright-angle triangle column light guide block 109, of which a slopedsurface is adhesively attached to the side surface of the twoaforementioned prisms 107 and 108, with the bottom surface of the lightguide block 109 facing upwards.

A light absorber 110 is disposed on the side surface of the prisms107/108 opposite the side to which the light guide block 109 isattached.

A light source optical system 104 disposed on the bottom part of thelight guide block 109 has an optical axis of the light source opticalsystem 104 vertically aligned. The light source optical system 104comprises a collimator lens 111; a dichroic filter 112 reflecting onlyred wavelength light and transmitting only the lights of green and bluewavelengths; a support mirror 113; two condenser lenses 114 (i.e., 114 aand 114 b); a color wheel 115 constituted by four color filtersalternately placing a color filter that transmits only green wavelengthlight and a color filter that transmits only blue wavelength light; tworod integrators 116 (i.e., 116 a and 116 b); two condenser lenses 117(i.e., 117 a and 117 b); and two condenser lenses 118 (i.e., 118 a and118 b).

The light projected from the light source 105 is transmitted first tothe dichroic filter 112 via the collimator lens 111 of the light sourceoptical system 104. The dichroic filter 112 reflects only the red lightemitted from the light source 105, while only the green light as well asblue light is transmitted through the dichroic filter 112.

The red light reflected by the dichroic filter 112 is further reflectedby the support mirror 113, and is incident to the SLM 101 a, positionedright below the prism 107, by way of the condenser lens 114 a, rodintegrator 116 a, condenser lens 117 a, condenser lens 118 a, lightguide block 109, and prism 107.

Meanwhile, the green and blue lights, having transmitted through thedichroic filter 112, are incident to the color wheel 115 via thecondenser lens 114 b. The color wheel 115 transmits either the green orblue light, depending on a color filter inserted into the light path.The green or blue light, having transmitted through the color wheel 115,is incident to the SLM 101 b, positioned right below the prism 108, byway of the rod integrator 116 b, condenser lens 117 b, condenser lens118 b, light guide block 109, and prism 108.

The red light projected to the SLM 101 a is reflected vertically upwardin the prism 107 as reflection light 119. When the mirror of the mirrorelement is in an ON state, the red reflection light 119 is furtherreflected by the outer side surface of the prism 107, is incident to theprojection lens 106, and is projected onto a screen 121. When the mirrorof the mirror element is in an OFF state, the light is reflected towardsthe light absorber 110 in the prism 107 as a reflection light 122 and isabsorbed by the light absorber 110.

Meanwhile, the green or blue light, having been incident to the SLM 101b, is reflected vertically upward in the prism 108 as a reflection light120. When the mirror of the mirror element is in the ON state, thereflection light 120 is further reflected by the outer side surface ofthe prism 108 and then the joined surface thereof, is incident to theprojection lens 106 by way of the same light path as the red reflectionlight, and is projected onto the screen 121. When the mirror of themirror element is in an OFF state, the light is reflected towards thelight absorber 110 in the prism 108 as a reflection light 123 and isabsorbed by the light absorber 110.

Alternately, the synthesis optical system 103 can also be implemented asa Philips prism and a polarization beam splitter (PBS), in addition tothe optical components according to the configuration described above inthe present embodiment.

As described above, the SLM 101 a is irradiated only with red light andthe SLM 101 b is irradiated only with green or blue light, so that themodulation light respectively modulated by the two SLMs 101 aresynthesized and condensed in the color synthesis optical system 103, asdescribed above. The condensed lights are enlarged by the projectionlens 106, and are projected onto the screen 121 in the video imagedisplay apparatus according to the present embodiment.

FIG. 3 is a functional block diagram illustrating the systemconfiguration of a video image display apparatus comprising a timingcontrol apparatus according to the present embodiment.

The video image display apparatus according to the present embodimentcomprises an image signal input unit 131, a frame buffer 132, an SLMcontroller 133, a sequencer 134, a motor unit 135, a photo detector (PD)136, a light source control unit 137, and a light source drive circuit138.

The image signal input unit 131 receives an image signal extracted froma video image signal incoming from an external device (not shown in thedrawing) converts image signal into image data.

The frame buffer 132 retains the image data converted by the imagesignal input unit 131. The present embodiment is configured to enablethe frame buffer 132 to retain image data of multiple frames.

The SLM controller 133 applies the image data received from the framebuffer 132 to generate SLM control data (i.e., display data) forcontrolling the mirrors in the mirror elements to operate in the ON/OFFor intermediate states in SLM 101 a and SLM 101 b. Further, the SLMcontroller 133 also controls the display start position of the SLM 101.It is possible to start displaying, for example, from the center or theportion of mirror array in each of the SLM depending on the mode.However, the display usually starts from the top end of the SLM 101.

The sequencer 134 is implemented with a microprocessor to control theoperational timing of the overall apparatus. The microprocessor maycontrol the readout timing of image data from the frame buffer 132, theoperational timing of the two SLMs, and the operational timing of thecolor wheel 115. The motor unit 135 controls the rotation speed of thecolor wheel 115 in accordance with a control signal from the sequencer134. The PD 136 is a position detection device for detecting the angularposition of the rotating color wheel 115 and angular position asdetected is outputted to the sequencer 134 as a wheel index signal. Thelight source control unit 137 controls the light source drive circuit138 in accordance with a control signal from the sequencer 134, and thelight source drive circuit 138 controls the emission operation of thelight source 105 in accordance with the aforementioned control.

FIG. 4 is a functional block diagram for showing the internalconfiguration of the sequencer 134 according to the present embodiment.The sequencer 134, according to the present embodiment, comprises aclock frequency generation unit 141, a master clock generation unit 142,a frame start signal generation unit 143, a phase comparator 144, alow-pass filter 145, a data output control unit 146, and a pointercontrol unit 147. The clock frequency generation unit 141 generates asystem clock signal. The master clock generation unit 142 generates, inaccordance with the set frequency, a master clock signal constituting areference clock for transferring image data to the SLM controller 133from the system clock signal generated by the clock frequency generationunit 141. The frame start signal generation unit 143 generates, inaccordance with the set frame rate, a frame start signal from the masterclock generated by the master clock generation unit 142. The phasecomparator 144 receives, as inputs, a wheel index signal output from thePD 136 and the frame start signal generated by the frame start signalgeneration unit 143, and outputs the difference in phases between bothsignals as an analog signal. Note that the PD 136 is provided to detecta black pattern 148 provided at a reference position on the color wheel115 and outputs the detection signal as a wheel index signal. Further,the color wheel 115 is configured to turn one revolution within a periodof displaying image data in the volume of one frame in a synchronousstate.

The low-pass filter 145 eliminates a high frequency component from ananalog signal output from the phase comparator 144 and outputs theresultant signal. Furthermore, the motor unit 135 includes a motordriver 149 and a motor 150. The motor driver 149 controls the rotationspeed of the motor 150 in accordance with the output of the low-passfilter that in turn rotates the color wheel 115 in accordance with theoutput of the low-pass filter. Furthermore, the motor 150 comprises aspeed detection device using a Hall element (not shown in the drawing)to control the motor driver and also control the rotation speed of themotor 150 under a target speed, in accordance with the output of thespeed detection device. The rotation speed of the color wheel 115 iscontrolled to eliminate the phase difference between the wheel indexsignal and frame start signal and controls the rotation of the colorwheel 115 at a rotation speed in accordance with the target rotationspeed of the motor 150.

The data output control unit 146 controls the image data output from theframe buffer 132 according to whether or not the phase differencebetween the wheel index signal output from the PD 136 and the framestart signal generated by the frame start signal generation unit 143 issmaller than a predefined value.

The pointer control unit 147 controls the write position (i.e., thewrite address) of the image data to the frame buffer 132 according tothe volume of one frame. The pointer control unit 147 further controlsthe read position (i.e., the read address) of image data according tothe volume of one frame from the frame buffer 132 on the basis of avertical synchronous signal (noted as “VSYNC” hereinafter) extractedfrom the video image signal incoming from an external device (not shownin the drawing) and of the frame start signal generated by the framestart signal generation unit 143. Here, the write position of image databy the volume of one frame is instructed by the value of a write pointer(WP) representing the write address. The read position of image data bythe volume of one frame is instructed by the value of a read pointer(RP) representing the read address. Note that the frame buffer 132secures a region to retain the image data by the volume of multipleframes simultaneously, and therefore, the possible values of the WP andRP are determined on the basis of the total number of pieces of imagedata by the volume of one frame because the frame buffer 132 is providedfor retaining multiple frame of data simultaneously. The presentembodiment defines the maximum value among the possible values of the WPand RP as the Max.

A timing control method carried out by a timing control apparatus in avideo image display apparatus according to the present embodiment isdescribed below.

FIG. 5 is a flow chart for showing the operation processes of theabove-described data output control unit 146 in more details.

The data output control unit 146 first determines whether or not a framestart signal has been inputted (S101). If the data output control unit146 determines that no signal has been inputted, it repeats thedetermination process. If the data output control unit 146 determinesthat a frame start signal has been inputted, it then compares the phasebetween the frame start signal and wheel index signal (S102) anddetermines whether or not the phase difference between the two signalsis smaller than a predefined value (S103), which is defined as 5 μs forthe present embodiment. If the difference is smaller than a predefinedvalue, the data output control unit 146 controls the data output so thatthe image data from the frame buffer 132 is simultaneously outputtedwith the frame start signal (S104). If the difference between the twosignals is not smaller than the predefined value, the data outputcontrol unit 146 executes a control so that no image data is outputtedfrom the frame buffer 132 (S105). Upon completion of the process of S104or S105, the process returns to S101.

The above-described process controls the output of the image data whenthe phase difference between a frame start signal and a wheel indexsignal is smaller than a predefined value when the two signals aresynchronized with each other. The processes further suspend an output ofthe image data when the aforementioned phase difference is greater thanor equal to the predefined value, that is, when the two signals are notsynchronized.

Therefore, the control processes stop the output of the image data fromthe frame buffer 132 (in the case of S105), and the mirrors of allmirror elements of the two SLMs are controlled to operate in the OFFstate.

FIG. 6 is a timing chart for showing an exemplary operation process ofthe data output control unit 146 of FIG. 5.

As illustrated in FIG. 6, if the phase difference T between a framestart signal and a wheel index signal greater than or equal to 5 μs(i.e., T₁≧5 μs and T₂≧5 μs), the frame buffer is controlled to stop anoutput of the image data (refer to “image data to SLM controller” being“OFF” on the far left of FIG. 6). If the phase difference between thetwo signals is smaller than 5 μs, the frame buffer 132 is controlled tooutput the image data (refer to “image data to SLM controller” being“data n”, “data n+1”, “data n+2” and “data n+3” in FIG. 6).

Note that while the present embodiment is configured to determinewhether or not to output image data from the frame buffer 132 on thebasis of a predefined value (i.e., 5 μs), the predefined value can beset at another arbitrary value. The control process further allows theflexibilities of changing the predefined values in accordance with thevideo image display apparatus used.

FIG. 7 is a flow chart showing, in detail, the operation of theabove-noted pointer control unit 147. It is assumed that WP and RP areinitially set at Max, before the present process flow. Further assumedis that the signal inputted first to the pointer control unit 147 afterstarting the present flow is VSYNC.

The pointer control unit 147 begins by determining whether a VSYNC isinputted, a frame start signal is inputted, or neither is inputted(S201). If it is determined in S201 that neither is inputted, thedetermination process is repeated.

In contrast, if it is determined in S201 that VSYNC is inputted, thenthe pointer control unit 147 determines whether or not the value of WPis Max. (WP=Max.) (S202). Specifically, if the result is “yes”, thevalue of WP is set at “0” (WP=0) to update the write position of theframe buffer 132 (S203). If the result is “no”, a value corresponding tothe image data by the volume of one frame is added to the value of WP(WP=WP+one-frame data) to update the write position of the frame buffer132 (S204). Note that a value corresponding to the image data by thevolume of one frame is added to the value of WP every time a VSYNC isinput in S204, and therefore, the value of WP also corresponds to thenumber of times VSYNC is inputted. Then, upon completion of S203 orS204, the process returns to S201.

Meanwhile, if it is determined in S201 that a frame start signal isinputted, the pointer control unit 147 then determines whether or notthe value of RP is Max (RP=Max) (S205). Here, if the result is “yes”,the value of RP is set at “0” (RP=0) to update the read position of theframe buffer 132 (S206). If the result is “no”, a value corresponding tothe image data by the volume of one frame is added to the value of RP(RP=RP+one-frame data) to update the read position of the frame buffer132 (S207). Note that a value corresponding to the image data by thevolume of one frame is added to the value of RP every time a frame startsignal is input in S207, and therefore, the value of RP also correspondsto the number of times the frame start signals are inputted.

After S206 or S207, the pointer control unit 147 determines whether ornot the value of RP is “0” and whether the value of WP is Max (RP=0 andWP=Max) (S208). If the result is “yes”, the value of RP is set at Max(RP=Max) to update the read position of the frame buffer 132 (S209), andthen the process returns to S201.

In contrast, if the result of S208 is “no”, the pointer control unit 147then determines whether the value of RP is Max and whether the value ofWP is “0” (RP=Max and WP=0); it also determines whether the value of RPis Max and whether the value of WP is equal to a value obtained byadding a value corresponding to the image data by the volume of oneframe to “0” (RP=Max and WP=(0+one-frame data) (S210). If the result ofS210 is “RP=Max and WP=(0+one-frame data)”, the value of RP is set at“0” (RP=0) to update the read position of the frame buffer 132 (S211),and the process returns to S201. If the result of S210 is “RP=Max andWP=0”, the process returns to S201. If the result of S210 is “RP=Max andWP≠0 and WP≠(0+one-frame data)”, then the pointer control unit 147compares the value of RP and the value of WP, and determines whether thevalue of RP is no less than the value of WP (RP≧WP), or the value of RPis smaller than a value obtained by subtracting a value corresponding tothe image data by the volume of one frame from the value of WP(RP<(WP−one-frame data)), or neither of the aforementioned cases((WP−one-frame data)≦RP<WP) (S212).

Note that the comparison between the value of RP and the value of WPperformed in S212 is actually carried out by a comparison unitinternally comprised in the pointer control unit 147. If the result ofS212 is “RP≧WP”, a value corresponding to the image data by the volumeof one frame is subtracted from the value of RP (RP=RP−one-frame data)to update the read position of the frame buffer 132 (S213), and theprocess then returns to S201. If the result of S212 is “RP<(WP−one-framedata)”, a value corresponding to the image data by the volume of oneframe is added to the value of RP (RP=RP+one-frame data) to update theread position of the frame buffer 132 (S214), and the process thenreturns to S201. If the result of S212 is “(WP−one-frame data)≦RP<RP”,the process then returns to S201.

Note that the value of WP is updated in S203 or S204 in this presentflow chart, and the image data by the volume of one frame is written tothe frame buffer 132 in accordance with the update value of WP.

Furthermore, when the value of RP is updated in S209, S211, S213, andS214, the image data by the volume of one frame is read from the framebuffer 132 in accordance with the update value of RP. Furthermore, ifthe result of S210 is “RP=Max and WP=0”, or if the result of S212 is“(WP−one-frame data)≦RP<WP”, the image data by the volume of one frameis read from the frame buffer 132 in accordance with the value of RPupdated in S206 or S207. However, these readouts of data are carried outonly when the data output control unit 146 controls the output of imagedata, as described above.

In these processes, if “RP≧WP” is determined in S212, the image data bythe volume of one frame, which is the same as the image data by thevolume of one frame that was outputted to the SLM controller 133 fromthe frame buffer 132, is outputted to the SLM controller 133.Furthermore, if “RP<(WP−one-frame data)” is determined in S212, thereadout of the image data by the volume of one frame that was writtenimmediately prior to the image data by the volume of one frame lastwritten to the frame buffer 132 will not be performed. Therefore, thereadout of one piece of the image data by the volume of one frame willbe skipped.

FIGS. 8 and 9 are timing charts for showing such an exemplary operationof the pointer control unit 147 shown in FIG. 7.

Specifically, the value of RP (“read pointer”) shown in FIGS. 8 and 9 as“N+2”, as, indicates that the value of RP is obtained by adding a valuecorresponding to the image data by the volume of (N+2) frames to “0”(i.e., RP=0+(N+2)-frame data). Furthermore, the value of WP (“writepointer”) is obtained in a similar manner.

FIG. 8 illustrates the case in which the frequency of VSYNC is higherthan the frequency of the frame start signal. In this example;

In the time period from time t₁ to time t₂: if the determination resultof the above described S212 is “(WP−one-frame data)≦RP<WT,” the imagedata by the volume of one frame is written to the frame buffer 132sequentially, in accordance with the value of WP that is updated in theabove described S204. The process is in synchronous with the VSYNC andalso the image data by the volume of one frame is read from the framebuffer 132 sequentially in accordance with the value of RP that isupdated in the above described S207 in synchronous with the frame startsignal.

At time t₂: when a frame start signal is inputted, the value of RP isupdated to “N+5” in the above-described S207. In this event, the valueof WP is “N+7”, causing the determination result of the above describedS212 to be “RP<(WP−one-frame data)”, and therefore, the value of RP isupdated to “N+6” in the above described S214. Therefore, the image databy the volume of one frame written in accordance with the value ofWP=“N+5” is not read and the readout is skipped.

Accordingly, if the frequency of VSYNC is higher than the frequency of aframe start signal, one frame of image data is skipped and not readunder the above described condition when “RP<(WP−one-frame data)”applies.

In contrast, FIG. 9 illustrates the case in which the frequency of VSYNCis lower than the frequency of a frame start signal.

At t₃: when a frame start signal is inputted, the value of RP is updatedto “N+1” in the above-described step S207. In this event, the value ofWP is also “N+1”, causing the determination result of theabove-described S212 to be “RP≧WP”, and therefore, the value of RP isupdated to “N” in the above-described step S213. Therefore, one frame ofimage data that was last outputted to the SLM controller 133 from theframe buffer 132. Specifically, one frame of the image data same as theone frame of image data that has been read in accordance with the valueof RP=“N”, are transferred to the SLM controller 133.

Before reach the time t₄: the determination process of theabove-described step S212 generates a result of “(WP−one-framedata)≦RP<WP”, and therefore, one frame of the image data is written tothe frame buffer 132 sequentially, in accordance with the value of WPupdated in the above described S204 in synchronous with the VSYNC.Furthermore, one frame of the image data is read from the frame buffer132 sequentially in accordance with the value of RP updated in theabove-described step S207 in synchronous with the frame start signal.

Therefore, if the frequency of a VSYNC is lower than the frequency of aframe start signal, one frame of the image data same as one frame of theimage data most recently transferred from the frame buffer 132 to theSLM controller 133, is transferred once more to the SLM controller 133when the above described condition “RP≧WP” applies.

According to the present embodiment described above, the video imagedisplay apparatus is configured to carry out operations based on a framestart signal individually generated within the sequencer for controllingthe rotation of the color wheel 115, the readout of image data from theframe buffer 132, and the operation of the two SLMs 101. Thereby theoperation of the apparatus will not depend on an externally inputtedsynchronous signal (VSYNC). Therefore, it is not required to configure acircuit responsive to various frequencies of externally inputtedsynchronous signals, and the circuit can be accordingly simplified. Itis further possible to stably maintain the operations of the apparatuseven if the externally inputted synchronous signals are unstable.

SECOND EMBODIMENT

FIG. 10 is a functional block diagram for illustrating the opticalcomponents of a video image display apparatus that includes an SLMcontrol apparatus according to a second preferred embodiment of thepresent invention. A color synthesis optical system 103 is illustratedin FIG. 10 as a top view in the upper portion and a rear view in thelower portion of FIG. 10.

The video image display apparatus according to the present embodimentcomprises a device package 102, containing two spatial light modulators(SLMs) 101 (i.e., 101 a and 101 b) accommodated as an integratedpackage; a color synthesis optical system 103; a light source opticalsystem 201; a light source 202; and a projection lens 106. Note that thedevice package 102 in which two spatial light modulators (SLMs) 101 aresituated, the color synthesis optical system 103, and projection lens106 are the same as those shown in FIGS. 2A through 2C, and thereforefurther descriptions are not provided here. The light source opticalsystem 201 comprises three condenser lenses 203 (i.e., 203 a, 203 b, and203 c), two-rod integrators 116 (i.e., 116 a and 116 b), two condenserlenses 117 (i.e., 117 a and 117 b), and two condenser lenses 118 (i.e.,118 a and 118 b).

The light source 202 comprises a red laser light source 202 a foremitting a laser light in the wavelength of red (simply noted as “redlaser light” hereinafter), a green laser light source 202 b for emittinga laser light of the wavelength of green (simply noted as “green laserlight” hereinafter), and a blue laser light source 202 c for emitting alaser light of the wavelength of blue (simply noted as “blue laserlight” hereinafter). Alternately, the present embodiment may beconfigured to implement a light emitting diode (LED) light sourceinstead of the laser light source.

According to the present embodiment, the red laser light source 202 aemits the red laser light to project through the rod integrator 116 a,condenser lens 117 a, condenser lens 118 a, light guide block 109, andprism 107 via the condenser lens 203 a and is incident to the SLM 101 adisposed right below the prism 107. The red laser light is reflectedfrom the SLM 101 a, and transmitted through the same light path asdescribed with reference to FIGS. 2A through 2C, and therefore furtherdescriptions are not provided here.

Meanwhile, the green laser light source 202 b emits the green laserlight for projecting through the rod integrator 116 b, condenser lens117 b, condenser lens 118 b, light guide block 109, and prism 107 viathe condenser lens 203 b and is incident to the SLM 101 b disposed rightbelow the prism 107. Similarly, the blue laser light source 202 c emitsthe blue laser light for projecting through the rod integrator 116 b,condenser lens 117 b, condenser lens 118 b, light guide block 109, andprism 107 via the condenser lens 203 c and is incident to the SLM 101 bpositioned right below the prism 107. According to the presentembodiment, the green laser light and blue laser light are respectivelyemitted in a time sequential manner from the green laser light source202 and blue laser light source 202 c. The light path of the green laserlight and blue laser light reflected from the SLM 101 b, is the same asthe light path of the green light or blue light reflected from the SLM101 b as that described with reference to FIGS. 2A through 2C, andtherefore further descriptions are not provided here.

FIG. 11 is a functional block diagram illustrating the systemconfiguration of a video image display apparatus comprising an SLMcontrol apparatus according to the present embodiment.

The video image display apparatus according to the present embodimentcomprises an image signal input unit 131, a frame buffer 132, an SLMcontroller 211, a sequencer 212, a light source control unit 213 and alight source drive circuit 214. Note that the image signal input unit131 and frame buffer 132 are the same as those shown in FIG. 3 andtherefore further descriptions are not provided here.

The SLM controller 211 generates SLM control data (i.e., display data)for controlling the mirror in each of the mirror elements to operate inthe ON state, the OFF state, and an oscillation state for the mirror ofthe mirror element in the SLM 101 a. The SLM controller 211 furthergenerates SLM control data (i.e., display data) for controlling themirror in each of the mirror elements to operate in the ON control, OFFcontrol and oscillation state for the mirror of the mirror element inthe SLM 101 b. The SLM controller 211 applies the image data read fromthe frame buffer 132 and generates data to control the SLMs 101.Therefore, the SLM controller 211 digitally controls two SLMs 101 bytransmitting the respective pieces of SLM control data to thecorresponding SLMs 101.

The sequencer 212 comprises a microprocessor and related components tocontrol the operational timing of the overall apparatus. The sequencer212 controls the operational timing of the two SLMs 101 and the timingof the three laser light sources 202.

The light source control unit 213 controls the light source drivecircuit 214, in accordance with the control signal received from thesequencer 212, and controls the emitting operation of the laser lightsource 202, in accordance with the light source drive circuit 214.Therefore, the light source control unit 213 controls the illuminationlights incident to SLM 101 a and SLM 101 b.

Particularly, the present embodiment is configured with each of the twoSLMs 101 comprises a mirror element array 221, a column driver 222, anda row driver 223. The mirror element array 221 includes a plurality ofmirror elements arranged in a grid-like fashion generally referred to asmirror array with the mirror elements disposed at the positions wherethe individual bit lines vertically extended from the column driver 222intersects with the word lines horizontally extended from the row driver223. The SLM control data (i.e., display data) outputted from the SLMcontroller 211 is inputted to the column driver 222. The row driver 223receives a timing signal outputted from the sequencer 212 to control theoperation of the row.

FIG. 12 is a side cross sectional diagram for illustrating the circuitconfiguration of each mirror element. FIG. 12 shows an OFF capacitor 232a connected to the OFF electrode 231, and the OFF capacitor 232 aconnected via a gate transistor 233 a to a bit line 234 a and a wordline 235. An ON capacitor 232 b is connected to the ON electrode 236,and the ON capacitor 232 b is connected via a gate transistor 233 b to abit line 234 b and a word line 235 by way of a gate transistor 233 b.Specifically, the OFF capacitor 232 a and gate transistor 233 aconstitute a memory cell having a Dynamic Random Access Memory (DRAM)structure, as does the ON capacitor 232 b and gate transistor 233 b.

The turning on and off of the gate transistor 233 a and gate transistor233 b are controlled via the word line 235.

Specifically, the mirror elements lined up on one horizontal row in linewith an arbitrary word line 235 are simultaneously selected, and thecharging, and discharging, of the charge in the OFF capacitor 232 a andON capacitor 232 b are controlled via the bit lines 234 a and 234 b,respectively. Thereby, the ON, OFF, and oscillation of the mirror 237 ofan individual mirror element on one horizontal row is controlled.

A description of the control for the mirror 237 under the ON, OFF, andoscillation is provided in detail with reference to FIGS. 13A through13C.

FIG. 13A is a side cross sectional diagram and an associated timingdiagram for showing the state of the mirror 237 controlled to operate inan ON state. FIG. 13B is a side cross sectional diagram and anassociated timing diagram for showing the state of the mirror 237controlled to operate in an OFF state. FIG. 13C is a side crosssectional diagram and an associated timing diagram for showing the stateof the mirror 237 controlled to operate in oscillation state). In eachdrawing, a cross-section of the mirror element in each state is shown onthe left side of the figure, and the operation waveform (i.e., thecontrol waveform) of the mirror 237 in each state is shown on the rightside of the figure. The operation waveform of the mirror 237 in eachstate also corresponds to the output state of light to the projectionlight path reflected by the mirror 237 in each respective state.

As shown in FIGS. 13A through 13C, each mirror element is supported onan elastic hinge 244 extended from an electrode 242. Each mirror elementfurther includes the above described OFF electrode 231 and ON electrode236 on a substrate 241, with each electrode covered with an insulationlayer 243. Note that the OFF electrode 231 and ON electrode 236 are alsoimplemented as address electrodes. An elastic hinge 244 is connected tothe hinge electrode 242, penetrating the insulation layer 243, and theelastic hinge 244 supports the deflectable mirror 237. The hingeelectrode 242 is grounded.

When a signal (0, 1) is applied to the memory cell (not shown in thedrawing here) of the mirror element the mirror 237 in the mirror elementis controlled to operate in an ON state as shown in FIG. 13A. A signal(0,1) causes a voltage Va [V] applied to the ON electrode 236 and avoltage 0 [V] applied to the OFF electrode 231. As the voltage Va [V] isapplied to the ON electrode 236, the mirror 237 is drawn by a Coulombforce in the direction of the ON electrode 236. The mirror 237 isdeflected to a position abutting the insulation layer 243 of the ONelectrode 236 for reflecting the incident light towards a projectionlight path. The state of the mirror element and that of the mirror 237in this event are referred to as an ON state, and the operation of themirror element and that of the mirror 237 in such a manner is referredto as an ON operation.

When the mirror 237 is controlled to be OFF, a signal (1, 0) is given tothe memory cell (not shown in the drawing here) of the mirror element,as shown in FIG. 13B. This causes a voltage Va [V] to be applied to theOFF electrode 231 and a voltage 0 [V] to be applied to the ON electrode236. As a result, the mirror 237 is drawn by a Coulomb force in thedirection of the OFF electrode 231, to which the voltage Va [V] isapplied, and is tilted to a position abutting the insulation layer 243of the OFF electrode 231. This causes the incident light to be reflected(i.e., deflected) by the mirror 237 in a direction other than theprojection light path. The state of the mirror element and that of themirror 237 in this event are referred to as the OFF state, and theoperation of the mirror element and that of the mirror 237 in such amanner is referred to as an OFF operation.

As shown in FIG. 13C, when the mirror 237 is controlled to operate in anoscillation state, a signal (0, 0) is applied to the memory cell (notshown in the drawing here) of the mirror element when the mirror 237 isin the OFF state. This causes a voltage 0 [V] to be applied to bothelectrodes 231 and 236. As a result, the Coulomb force that has beengenerated between the mirror 237 and OFF electrode 231 is withdrawn,thus causing the mirror 237 to start a free oscillation, having anoscillation frequency depending on the elasticity of the elastic hinge244. During the time when the mirror is operated in the oscillationstate, the incident light is repeatedly reflected (i.e., deflected) bythe mirror 237 between the ON direction and the OFF direction. The stateof the mirror element and that of the mirror 237 in this event arereferred to as the oscillation state, and the operation of the mirrorelement and that of the mirror 237 in such a manner is referred to as anoscillating operation.

Additionally, the mirror 237 can start to operate in an oscillationstate when the mirror 237 is initially in the ON state.

FIG. 13C illustrates the mirror element operates in an oscillationstate. The mirror alternately oscillates between directions of the ONstate and OFF state. The oscillation amplitude of the mirror is themaximum amplitude. The mirror can also be set to have a smalleramplitude of oscillation. This is accomplished by applying a signal (0,0) to a memory cell (not shown in the drawing here) of the mirrorelement just before the mirror 237 is tilted to a position abutting theinsulation layer 243 of the ON electrode 236 or that of the OFFelectrode 231, after starting the above described ON control or OFFcontrol for the mirror 237. An alternate method is to apply a signal (1,0) again to the memory cell for a desired period of time immediatelyafter giving a signal (0, 0) to the memory cell (not shown in thedrawing here) of the mirror element when the mirror 237 is in the OFFstate.

The following is a description of an SLM control method carried out inthe video image display apparatus that comprises an SLM controlapparatus according to the present embodiment.

According to the present embodiment, the SLM controller 211 of the videoimage display apparatus controls SLM 101 b in coordination with thelight source control unit 213, which controls the laser light source 202during the period in which the SLM controller 211 controls SLM 101 a inaccordance with the image data on the basis of a video image signal.Specifically, the SLM controller 211 maintains the operational state ofSLM 101 b in a constant state during the period in which the SLMcontroller 211 controls SLM 101 a in accordance with the image data onthe basis of a video image signal and also in which the light sourcecontrol unit 213 switches over the color of the laser light (i.e., anillumination light) incident to SLM 101 b. The constant state maintainedin SLM 101 b in this case signifies that the operational state of eachmirror element on the SLM 101 b is maintained in the ON state, OFFstate, or the oscillation state. For example, the operational state of amirror element can be maintained by maintaining the data accumulated inthe memory cell that comprises a DRAM structure, or by overwriting thememory cell with the same data of the last writing cycle in the circuitconfiguration shown in FIG. 12.

FIGS. 14A, 15A, 16A, 17A, 18A, 19A and 20A are diagrams showingexemplary timing diagrams for controlling the two SLMs 101 performed bythe SLM controller 211 described above. Each figure shows an exemplarytiming diagram for controlling a pixel as a representative pixelimplementing control processes shown in FIGS. 14B, 15B, 16B, 17B, 18B,19B and 20B).

In these exemplary control processes, an incident red laser light ismodulated in accordance with the SLM control data used for SLM 101 a(that is, the red-use SLM control data) sent from the SLM controller211. Furthermore, one frame period is divided into two sub-frames sothat the blue laser light incident during the one sub-frame is modulatedby SLM 101 b in accordance with the SLM control data used for the bluelight. Furthermore, the green laser light incident during the othersub-frame period is modulated by SLM 101 b in accordance with the SLMcontrol data used for the green light.

In these figures, the transition period spans the period from which themodulation of SLM 101 b is controlled on the basis of the blue-use SLMcontrol data sent from the SLM controller 133 to a period in which themodulation of SLM 101 b is controlled on the basis of the green-use SLMcontrol data sent from the SLM controller 133.

The exemplary control processes shown in FIGS. 14A and 15A are appliedto maintain the operational state of all mirror elements of SLM 101 b inthe ON state during the period when the SLM controller 211 controls SLM101 a in accordance with the image data on the basis of a video imagesignal. That is a period when the red laser light incident to the SLM101 a is modulated in accordance with the SLM control data used for SLM101 a) and also when the light source control unit 213 switches thelaser lights incident to the SLM 101 b from the blue light to greenlight (i.e., the period T₃ in the example of FIG. 14A; and the period T₄in the example of FIG. 15A). Specifically, the present embodimentimplements a laser light source as the light source, and therefore, theperiod T₃ shown in FIG. 14A and the period T₄ shown in FIG. 15A are veryshort periods. In both of these transition periods, the intensity ofprojection light from SLM 101 b is held constant at the maximumintensity during the period in which the laser lights are controlled toswitch from the blue light to the green light.

Note that such control processes applied to the two SLMs 101 can beapplied not only to the video image display apparatus according to thepresent embodiment implemented with a laser light source but also to, avideo image display apparatus implemented with a lamp light source and acolor wheel.

FIGS. 14B and 15B are diagrams showing the exemplary controls for SLM101 b in such a case. Note that the exemplary control for SLM 101 a inthis case is the same that as shown in FIGS. 14A and 15A, and thereforethe drawing is not provided.

As shown in FIGS. 14B and 15B, the exemplary control in this case issuch that the operational state of all mirror elements of SLM 101 b ismaintained in the ON state during the period in which the SLM controller133 controls SLM 101 a in accordance with the image data on the basis ofa video image signal (i.e., the period in which the red light incidentto SLM 101 a is modulated in accordance with the SLM control data usedfor SLM 101 a) and also in which the color wheel 115 switches over thelight incident to SLM 101 b from the blue light to the green light(i.e., the blanking period T₅ shown in FIG. 14B and the blanking periodT₆ shown in FIG. 15B). In both of these periods, T₅ and T₆, theintensity of projection light from SLM 101 b is held constant at themaximum intensity during the period in which the light is controlled toswitch over from the blue light to the green light.

In the exemplary controls shown in FIGS. 16A, 17A, 18A and 19A, thecontrol is such that the operational state of all mirror elements of SLM101 b is maintained in the OFF state during the period in which the SLMcontroller 212 controls the SLM 101 a in accordance with the image dataon the basis of a video image data (i.e., the period in which the redlaser light incident to SLM 101 a is modulated in accordance with theSLM control data used for SLM 101 a) and also in which the light sourcecontrol unit 213 switches over the laser light incident to SLM 101 bfrom the blue light to the green light (i.e., period T₇ in FIG. 16A;period T₈ in FIG. 17A; period T₉ in FIG. 18A; and period T₁₀ in FIG.19A).

Note that the present embodiment is configured to use a laser lightsource as the light source, and therefore the above-described periodsT₇, T₈, T₉, and T₁₀ are all very short periods. During these periods,the intensity of projection light from SLM 101 b is held constant at “0”during the period in which the laser lights are switched from the bluelight to the green light.

The above-described control method applied to the two SLMs 101 of thevideo image display apparatus according to the present embodimentcomprising a laser light source can also be applied to a video imagedisplay apparatus according to the first embodiment implemented with alamp light source and a color wheel.

FIGS. 16B, 17B, 18B and 19B are timing diagrams for showing an exemplarycontrol process applied to the SLM 101 b. Note that the exemplarycontrol methods applied to the SLM 101 a in these cases are the same asthose shown in FIGS. 16A, 17A, 18A and 19A, and therefore the drawingsare not provided here.

FIGS. 16B, 17B, 18B and 19B show the exemplary control methods with theoperational state of all mirror elements of the SLM 101 b maintained inthe OFF state during the period when the SLM controller 133 controls SLM101 a in accordance with the image data on the basis of a video imagesignal (i.e., the period in which the red light incident to SLM 101 a ismodulated in accordance with the SLM control data used for SLM 101 a)and also in which the color wheel 115 switches the light incident to SLM101 b from the blue light to the green light (i.e., the blanking periodsT₁₁ in FIG. 16B, T₁₂ in FIG. 17B, T₁₃ in FIG. 18B, and T₁₄ in FIG. 19B).During the above-noted blanking periods T₁₁, T₁₂, T₁₃ and T₁₄, theintensity of projection light from the SLM 101 b is held constant at“0”.

In the exemplary control method shown in FIG. 20A, the operational stateof all mirror elements of SLM 101 b is maintained in the oscillationstate during the period when the SLM controller 211 controls SLM 101 ain accordance with the image data on the basis of a video image data(i.e., the period in which the red laser light incident to SLM 101 a ismodulated in accordance with the SLM control data used for SLM 101 a)and also in which the light source control unit 213 switches over thelaser light incident to SLM 101 b from the blue light to the green light(i.e., the period T₁₅ in the example of FIG. 20A). Note that the presentembodiment is configured to use a laser light source as light source,and therefore the above described period T₁₅ shown in FIG. 20A is a veryshort period. During the above-noted period T₁₅, the intensity ofprojection light from the SLM 101 b is held constant at an intermediatequantity (i.e., the intensity of light that is neither zero nor themaximum).

The above-described control methods applied to the two SLMs 101 of thevideo image display apparatus according to the present embodimentcomprising a laser light source can also be applied to a video imagedisplay apparatus implemented with a lamp light source and a colorwheel.

FIG. 20B is a timing diagram for showing an exemplary control methodapplied to the SLM 101 b. The control process applied to the SLM 101 ais the same as that shown in FIG. 20A, and the drawing is not providedhere.

FIG. 20B illustrates a control process with the operational state of allmirror elements of SLM 101 b maintained in the oscillation state duringthe period when the SLM controller 133 controls SLM 101 a in accordancewith the image data on the basis of a video image signal (i.e., theperiod in which the red light incident to SLM 101 a is modulated inaccordance with the SLM control data used for SLM 101 a) and also inwhich the color wheel 115 switches over the light incident to SLM 101 bfrom the blue light to the green light (i.e., the blanking period T₁₆shown in FIG. 20B). Also, during the blanking period T₁₆, the intensityof projection light from SLM 101 b is held constant at an intermediateintensity (i.e., the intensity of light that is neither zero nor themaximum).

As described above, the video image display apparatus according to thepresent embodiment is capable holding constant the intensity ofprojection light at various levels during the period when the color ofincident light is switched over in a time sequence, thereby making itpossible to prevent a degradation in the video image quality due to atemporary decrease in the intensity of projection light during theswitching period. Further, if the intensity of projection light isadjusted in accordance with the level of brightness of the video sceneto be displayed, when the SLM is controlled so that the intensity ofprojection light is held constant during the switching period. Theabove-described control methods can further prevent a degradation in thevideo image quality.

THIRD EMBODIMENT

A third preferred embodiment of the present invention comprises a videoimage display apparatus implemented with an SLM control apparatuscomprising the same optical components as those of the above describedvideo image display apparatus according to the second embodiment. Thevideo image display apparatus implements a different control method foroperating the video image display apparatus with different operationalsequences.

In the video image display apparatus according to the presentembodiment, the SLM controller 211 applies the image data read receivedfrom the frame buffer 132 to generate a piece of control data for SLM101 a for each sub-frame of multiple sub-frame periods obtained bydividing one frame period, and also generates a piece of control datafor SLM 101 b for each sub-frame of multiple sub-frame periods obtainedby dividing one frame period. Here, one sub-frame period related to thecontrol data for SLM 101 a and one sub-frame period related to thecontrol data for SLM 101 b may be the same, or the two periods may bedifferent from each other. If the configuration is such that onesub-frame period for SLM 101 a and one sub-frame period for SLM 101 bare the same, the start timing of the sub-frame period for SLM 101 a maybe set to be different from the start timing of the sub-frame period forSLM 101 b. Furthermore, when the display of SLM 101 b is started for anarea where the display is carried out using SLM 101 a, the area of theSLM 101 b corresponding to the display area of the SLM 101 a can alsoselected for starting the image display applying mirror elements in theselected area. Alternately, the start timing of display for SLM 101 bmay be matched to that of SLM 101 a. A discretionary word line of theSLM can be selected, as described above, and therefore the designationof the same address for selecting the respective word lines of SLM 101 aand SLM 101 b eliminates a need to provide a specific circuit, enablingthe implementation of the circuit disclosed in this application. Thisconfiguration makes it possible to reduce the occurrence of a shift indisplays between SLM 101 a and SLM 101 b.

Furthermore, the data of SLM 101 a and that of SLM 101 b may becontrolled to have different gradations and/or gamma characteristics.

Associated with the above-described methods, the light source controlunit 213 controls the light source drive circuit 214 to control theillumination lights incident to SLM 101 a and SLM 101 b for eachsub-frame period related to the control data for SLM 101 a and SLM 101b, respectively. Since only the red laser light is incident to SLM 101 bthe light source may be continuously turned on regardless of thesub-frame period related to the SLM 101 b. Specifically, the sequencer212 controls the above-described operational timings.

FIGS. 21 and 22 are timing diagrams for showing the operationalsequences of two SLMs 101 and an exemplary control process for laserlights incident to the two SLMs 101. Furthermore, FIGS. 23 and 24 aretiming diagrams for showing the operational sequences of two SLMs 101and an exemplary control process for laser lights incident to the twoSLMs 101 and also the colors of output lights (i.e., projection lights)that are projected onto a screen by the two SLMs 101. Specifically, eachfigure shows an exemplary control process of a representative pixel.

Specifically, for the convenience of description, FIGS. 21 through 24depict the period of switching over the colors of laser lights incidentto the SLM 101 a (e.g., the period T₁₇ shown in FIG. 21) and the periodbetween the end of the irradiation of laser light to the SLM 101 b inone sub-frame period and the start of the irradiation in the nextsub-frame (e.g., the period T₁₈ shown in FIG. 21) as a longer period;they are, however, very short periods. Further, for the convenience ofdescription, FIGS. 22 and 24 depict the shift between the start timingof one frame period related to the control data for SLM 101 a and thestart timing of one frame period related to the control data for SLM 101b as relatively large; it is, however, actually very small, to theextent that it is unrecognizable to a viewer.

The exemplary control process shown in FIG. 21 is implemented in a videoimage display apparatus wherein the SLM controller 211 generates controldata for SLM 101 a for each sub-frame period of four sub-frames,obtained by dividing one frame period into four parts; generates controldata for SLM 101 b for each sub-frame period of three sub-frame periods,obtained by dividing one frame period into three parts; and controls thetwo SLMs 101. The light source control unit 213 controls theillumination lights incident to SLM 101 a and SLM 101 b for eachsub-frame period related to the control data for SLM 101 a and SLM 101b, respectively. In this exemplary control process, the sub-frame periodrelated to the control data for SLM 101 a is different from thesub-frame period related to the control data for SLM 101 b.

By applying the above-described control process, FIG. 21 shows that thetiming of the period (e.g., the period T₁₇) when the colors of laserlights incident to the SLM 101 a are switched is different from thetiming of the period (e.g., the period T₁₈) between the end of theirradiation of laser light onto SLM 101 b in one frame period and thestart of the irradiation of laser light onto SLM 101 b in the nextsub-frame period. Thereby, the control processes suppress the phenomenaof color breakup.

FIG. 22 shows another exemplary control process. Specifically, the SLMcontroller 211 generates control data for SLM 101 a for each sub-frameperiod of four sub-frames subdivided from one frame period. The SLMcontroller 211 further generates control data for SLM 101 b for eachsub-frame period of the four sub-frame periods subdivided from one frameperiod. The SLM controller 211 further controls two SLMs 101. The lightsource control unit 213 controls the illumination lights incident to SLM101 a and SLM 101 b for each sub-frame period related to the controldata for SLM 101 a and SLM 101 b, respectively. In this exemplarycontrol process, however, one sub-frame period for applying the controldata to SLM 101 a is the same as one sub-frame period for applying thecontrol data to SLM 101 b. Therefore, the start timing of one sub-frameperiod for applying the control data to the SLM 101 a is different fromthe start timing of one sub-frame period for applying the control datato the SLM 101 b.

According to the above-described control process, FIG. 22 illustratesthat the timing of the period (e.g., the period T₁₉) when the colors oflaser lights incident to the SLM 101 a are switched over is alwaysdifferent from the timing of the period (e.g., the period T₂₀) betweenthe end of the irradiation of laser light onto SLM 101 b in one frameperiod and the start of the irradiation of laser light onto SLM 101 b inthe next one sub-frame period. Thereby, the control processes asdescribed suppress the color breakup phenomena.

The exemplary control process shown in FIG. 23 is basically the same asthe control process shown in FIG. 21. Specifically, the SLM controller211 generates control data for SLM 101 a for each sub-frame period offour sub-frames subdivided from one frame period. The SLM controller 211further generates control data for SLM 101 b for each sub-frame periodof three sub-frame periods subdivided from one frame period. The SLMcontroller 211 further controls the two SLMs 101. The light sourcecontrol unit 213 controls the illumination light incident to the SLM 101a and SLM 101 b for each sub-frame period for applying the control datato SLM 101 a and SLM 101 b, respectively. In this exemplary controlprocess, one sub-frame period for applying the control data to the SLM101 a is different from one sub-frame period related to the control datafor SLM 101 b.

As that illustrated in FIG. 21, the above-described control process cantherefore suppress the color breakup phenomenon.

FIG. 23 illustrates another exemplary control process. An output light(i.e., the projection light) projected on the screen 121 by the two SLMs101 may be either one of the complementary colors (i.e., yellow (Y) andmagenta (M)) or the three primary colors (i.e., red (R), green (G) andblue (B)). Furthermore, a period any one of the three primary colors oflight is projected in a period following the rule as set forth below: a)the period T₂₃ when the right of red (R) is projected between a periodwhen the light of either of the complementary colors is being projected;b) the period T₂₁ when the light of yellow is projected and a periodwhen the light of either of the complementary colors is projected, e.g.,the period T₂₂ in which the light of magenta is projected).

Furthermore, the exemplary control process arranges the cycle of periodswhen projecting any one of the three primary colors of light, e.g., thecycle of periods when projecting the light of R is different from thecycle of periods when projecting another one or two color lights of thethree primary colors (e.g., the cycle of periods when projecting thelight of blue or green lights.

Furthermore, the exemplary control process arranges the period whenprojecting any one of the three primary color lights, (e.g., the periodswhen projecting the red light is different from the period whenprojecting the light(s) of another one or two color lights of threeprimary colors, e.g., the period when projecting the blue or greenlight.

FIG. 24 illustrates another exemplary control process that is basicallythe same as the control process shown in FIG. 22. Specifically, the SLMcontroller 211 generates control data for SLM 101 a for each onesub-frame period of four sub-frames, subdivided from one frame period.The SLM controller further generates control data for the SLM 101 b foreach one sub-frame period of four sub-frame periods subdivided from oneframe period. The light source control unit 213 controls theillumination light to be incident to SLM 101 a and SLM 101 b for eachsub-frame period related to the control data for SLM 101 a and SLM 101b, respectively. In this exemplary control process, however, onesub-frame period for applying the control data for SLM 101 a is the sameas one sub-frame period for applying the control data for SLM 101 b,whereas the start timing of one sub-frame period for applying thecontrol data for SLM 101 a is different from the start timing of onesub-frame period for applying the control data to the SLM 101 b. Theabove-described control process as illustrated in FIG. 22 can thereforefurther suppress the color breakup phenomena.

FIG. 24 illustrates another exemplary control process wherein the outputlight, i.e., the projection light, that may comprise either one ofcomplementary colors (i.e., yellow (Y) and magenta (M)) and threeprimary colors of light (i.e., red (R), green (G) and blue (B)) isprojected on the screen 121 by the two SLMs 101. Furthermore, theexemplary control process arrange a period for projecting any one of thethree primary color lights by the following rules: a) projecting the red(R) light in the period T₂₆ between a period when projecting the lightof either of the complementary colors, b) projecting the magenta (M)light in the period T₂₄ and a period when projecting either of thecomplementary colors, e.g., the period T₂₅ when projecting the yellowlight.

Furthermore, the exemplary control arranges the cycle of periods forprojecting any one of the three primary color lights, e.g., the cycle ofperiods for projecting the light of R is different from the cycle ofperiods for projecting the light(s) of another one or two colors ofthree primary colors, e.g., the cycle of periods for projecting the blue(B) light.

Furthermore, the exemplary control process arranges the period forprojecting any one of the three primary colors of light, e.g., theperiods for projecting the red light is different from the period forprojecting the light(s) of another one or two colors of three primarycolors, e.g., the period for projecting the green (G) light.

As described thus far, the video image display apparatus according tothe present embodiment is configured to differentiate, in some or allcases, the timing of the period in which the colors of laser lightsincident to SLM 101 a are switched over from the timing of the periodbetween the end of the irradiation of laser light onto SLM 101 b in onesub-frame period and the start of the irradiation of the laser lightonto SLM 101 b in the next one sub-frame period. Thereby, the controlprocesses can suppress the color breakup phenomena.

Specifically, the description of the present embodiment has beenprovided by exemplifying the image display device as the video imagedisplay apparatus according to the second embodiment as the video imagedisplay apparatus; it is understood that control processes and systemconfiguration may also be utilized in different video displayapparatuses including but not limited to the video image displayapparatus according to the first embodiment.

While the present invention has been described in detail, the presentinvention, however, may of course be improved or modified in variousmanners possible within the spirit and scope of the present invention,and is not limited to the embodiments described above.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alternationsand modifications will no doubt become apparent to those skilled in theart after reading the above disclosure. Accordingly, it is intended thatthe appended claims be interpreted as covering all alternations andmodifications as fall within the true spirit and scope of the invention.

1. A video image display apparatus for displaying a video image inaccordance with a video image signal, comprising: a buffer for storingdata; a pointer control unit for generating a write pointer for pointingto a write starting address in the buffer for writing data to thebuffer, and a read pointer for pointing to a read starting address inthe buffer for reading data from the buffer; a comparison unit forcomparing the write starting address and the read starting address; anda data readout unit for controlling the read pointer according to acomparison result generated by the comparison unit.
 2. The video imagedisplay apparatus according to claim 1, wherein: the read startingaddress in the buffer is set to be equal to the read starting address ofan immediately previous read pointer if the write starting address inthe buffer is smaller than the read starting address according to thecomparison result generated by the comparison unit.
 3. The video imagedisplay apparatus according to claim 1, wherein: the read startingaddress in the buffer is set at to be equal to the write startingaddress if the write starting address is larger than the read startingaddress according to the comparison result generated by the comparisonunit.
 4. The video image display apparatus according to claim 1, furthercomprising: a pointer control unit for generating the write pointerbased on a synchronous signal of the video image signal.
 5. The videoimage display apparatus according to claim 1, wherein: a pointer controlunit for generating the read pointer based on a clock signal internal tothe video image display apparatus.
 6. The video image display apparatusaccording to claim 5, further comprising: a sequencer for controlling atiming for transmitting a data to a spatial light modulator (SLM) on thebasis of a clock signal.
 7. A buffer management method implemented in avideo image display apparatus for displaying images, comprising:controlling a write address in a buffer for writing input data thereto;controlling a read address in the buffer for reading display datatherefrom; comparing the write address and read address; and managing atransmission of the display data to a spatial light modulator (SLM)based on a comparison result of comparing the write address to the readaddress.
 8. The buffer management method according to claim 7, furthercomprising: comparing the write address with the read address before thedisplay data is read from the buffer, and retransmitting the displaydata transmitted in an immediate previous transmission if the writeaddress is smaller than the read address.
 9. The buffer managementmethod according to claim 7, wherein: comparing the write address withthe read address before the display data is read from the buffer, andtransmitting a latest data in the buffer to the SLM if the write addressis larger than the read address.
 10. The buffer management methodaccording to claim 7, further comprising: retaining data in the buffersufficient for at least two cycles of readout and data transmission tothe SLM.
 11. The buffer management method according to claim 7, furthercomprising: writing data to the buffer and reading display data from thebuffer asynchronously with each other.
 12. The buffer management methodaccording to claim 7, further comprising: controlling a color changeoverof illumination lights for projecting to the SLM in a time sequencecoincides with a timing sequence of reading display data from thebuffer.
 13. The buffer management method according to claim 12, wherein:skipping a transmission of data from the buffer to the SLM if adifference between a color change over time and a display data readouttime from the buffer is greater than or equal to a predefined value. 14.A video image display apparatus for displaying a video image inaccordance with a video image signal, comprising: a plurality of spatiallight modulators (SLMs); and a buffer for storing data on the basis ofthe video image signal, wherein said buffered is controlled for readingand transmitting data from said buffer to at least one of the SLMSasynchronous with writing data to the buffer, and said buffer iscontrolled to transmit data to at least another SLM with the datawritten synchronously with the data readout from the buffer.
 15. Thevideo image display apparatus according to claim 14, further comprising:a sequencer for controlling and asynchronously transmitting data fromthe buffer to each of the SLMs.
 16. The video image display apparatusaccording to claim 14, further comprising: a sequencer for controllingtimings of projecting lights of different wavelengths to an SLM fortransmitting the data in the buffer to the SLM with the data readasynchronous with the data written to the buffer.
 17. The video imagedisplay apparatus according to claim 14, further comprising: a lightsource controller for controlling and continuously projecting anillumination light of one wavelength an SLM for receiving the data fromthe buffer wherein the data are read in synchronous with the datawritten the buffer.